// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  gicr_lpi_regs_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/05/11 14:50:32 Create file
// ******************************************************************************

#ifndef __GICR_LPI_REGS_REG_OFFSET_FIELD_H__
#define __GICR_LPI_REGS_REG_OFFSET_FIELD_H__

#define GICR_LPI_REGS_GICR_CTLR_UWP_LEN           1
#define GICR_LPI_REGS_GICR_CTLR_UWP_OFFSET        31
#define GICR_LPI_REGS_GICR_CTLR_DPG1_LEN          1
#define GICR_LPI_REGS_GICR_CTLR_DPG1_OFFSET       25
#define GICR_LPI_REGS_GICR_CTLR_DPG0_LEN          1
#define GICR_LPI_REGS_GICR_CTLR_DPG0_OFFSET       24
#define GICR_LPI_REGS_GICR_CTLR_RWP_LEN           1
#define GICR_LPI_REGS_GICR_CTLR_RWP_OFFSET        3
#define GICR_LPI_REGS_GICR_CTLR_ENABLELPIS_LEN    1
#define GICR_LPI_REGS_GICR_CTLR_ENABLELPIS_OFFSET 0

#define GICR_LPI_REGS_GICR_IIDR_VERSION_LEN    32
#define GICR_LPI_REGS_GICR_IIDR_VERSION_OFFSET 0

#define GICR_LPI_REGS_COMMONLPIAFF_LEN            2
#define GICR_LPI_REGS_COMMONLPIAFF_OFFSET         24
#define GICR_LPI_REGS_GICR_TYPER_PROCNUM_LEN      16
#define GICR_LPI_REGS_GICR_TYPER_PROCNUM_OFFSET   8
#define GICR_LPI_REGS_GICR_TYPER_DPGS_LEN         1
#define GICR_LPI_REGS_GICR_TYPER_DPGS_OFFSET      5
#define GICR_LPI_REGS_GICR_TYPER_LAST_LEN         1
#define GICR_LPI_REGS_GICR_TYPER_LAST_OFFSET      4
#define GICR_LPI_REGS_GICR_TYPER_DIRECTLPI_LEN    1
#define GICR_LPI_REGS_GICR_TYPER_DIRECTLPI_OFFSET 3
#define GICR_LPI_REGS_GICR_TYPER_VLPIS_LEN        1
#define GICR_LPI_REGS_GICR_TYPER_VLPIS_OFFSET     1
#define GICR_LPI_REGS_GICR_TYPER_LPIS_LEN         1
#define GICR_LPI_REGS_GICR_TYPER_LPIS_OFFSET      0

#define GICR_LPI_REGS_GICR_TYPER_A3_LEN    8
#define GICR_LPI_REGS_GICR_TYPER_A3_OFFSET 24
#define GICR_LPI_REGS_GICR_TYPER_A2_LEN    8
#define GICR_LPI_REGS_GICR_TYPER_A2_OFFSET 16
#define GICR_LPI_REGS_GICR_TYPER_A1_LEN    8
#define GICR_LPI_REGS_GICR_TYPER_A1_OFFSET 8
#define GICR_LPI_REGS_GICR_TYPER_A0_LEN    8
#define GICR_LPI_REGS_GICR_TYPER_A0_OFFSET 0

#define GICR_LPI_REGS_GICR_STATUS_WORD_LEN    1
#define GICR_LPI_REGS_GICR_STATUS_WORD_OFFSET 3
#define GICR_LPI_REGS_GICR_STATUS_RWOD_LEN    1
#define GICR_LPI_REGS_GICR_STATUS_RWOD_OFFSET 2
#define GICR_LPI_REGS_GICR_STATUS_WRD_LEN     1
#define GICR_LPI_REGS_GICR_STATUS_WRD_OFFSET  1
#define GICR_LPI_REGS_GICR_STATUS_RRD_LEN     1
#define GICR_LPI_REGS_GICR_STATUS_RRD_OFFSET  0

#define GICR_LPI_REGS_GICR_WAKER_QUIESCENT_LEN         1
#define GICR_LPI_REGS_GICR_WAKER_QUIESCENT_OFFSET      31
#define GICR_LPI_REGS_GICR_WAKER_CHILDRENASLEEP_LEN    1
#define GICR_LPI_REGS_GICR_WAKER_CHILDRENASLEEP_OFFSET 2
#define GICR_LPI_REGS_GICR_WAKER_PROCESSORSLEEP_LEN    1
#define GICR_LPI_REGS_GICR_WAKER_PROCESSORSLEEP_OFFSET 1
#define GICR_LPI_REGS_GICR_WAKER_SLEEP_LEN             1
#define GICR_LPI_REGS_GICR_WAKER_SLEEP_OFFSET          0

#define GICR_LPI_REGS_GICR_SETLPI_PID_LEN    32
#define GICR_LPI_REGS_GICR_SETLPI_PID_OFFSET 0



#define GICR_LPI_REGS_GICR_CLRLPI_PID_LEN    32
#define GICR_LPI_REGS_GICR_CLRLPI_PID_OFFSET 0



#define GICR_LPI_REGS_GICR_PROBASER_L_LEN         20
#define GICR_LPI_REGS_GICR_PROBASER_L_OFFSET      12
#define GICR_LPI_REGS_GICR_PROSHAREABILITY_LEN    2
#define GICR_LPI_REGS_GICR_PROSHAREABILITY_OFFSET 10
#define GICR_LPI_REGS_GICR_PROCACHEABILITY_LEN    3
#define GICR_LPI_REGS_GICR_PROCACHEABILITY_OFFSET 7
#define GICR_LPI_REGS_GICR_PROIDBITS_LEN          5
#define GICR_LPI_REGS_GICR_PROIDBITS_OFFSET       0

#define GICR_LPI_REGS_GICR_PROBASER_H_LEN    16
#define GICR_LPI_REGS_GICR_PROBASER_H_OFFSET 0

#define GICR_LPI_REGS_GICR_PENDBASER_L_LEN         16
#define GICR_LPI_REGS_GICR_PENDBASER_L_OFFSET      16
#define GICR_LPI_REGS_GICR_PENDSHAREABILITY_LEN    2
#define GICR_LPI_REGS_GICR_PENDSHAREABILITY_OFFSET 10
#define GICR_LPI_REGS_GICR_PENDCACHEABILITY_LEN    3
#define GICR_LPI_REGS_GICR_PENDCACHEABILITY_OFFSET 7

#define GICR_LPI_REGS_GICR_PENDBASER_PTZ_LEN    1
#define GICR_LPI_REGS_GICR_PENDBASER_PTZ_OFFSET 30
#define GICR_LPI_REGS_GICR_PENDBASER_H_LEN      16
#define GICR_LPI_REGS_GICR_PENDBASER_H_OFFSET   0

#define GICR_LPI_REGS_GICR_INVLPI_PID_LEN    32
#define GICR_LPI_REGS_GICR_INVLPI_PID_OFFSET 0







#define GICR_LPI_REGS_GICR_SYNCR_BUSY_LEN    1
#define GICR_LPI_REGS_GICR_SYNCR_BUSY_OFFSET 0

#define GICR_LPI_REGS_GICR_MOVLPI_PID_LEN    32
#define GICR_LPI_REGS_GICR_MOVLPI_PID_OFFSET 0

#define GICR_LPI_REGS_GICR_MOVLPI_TA_LEN    32
#define GICR_LPI_REGS_GICR_MOVLPI_TA_OFFSET 0



#define GICR_LPI_REGS_GICR_MOVALL_TA_LEN    32
#define GICR_LPI_REGS_GICR_MOVALL_TA_OFFSET 0

#define GICR_LPI_REGS_GICR_CID0_LEN    32
#define GICR_LPI_REGS_GICR_CID0_OFFSET 0

#define GICR_LPI_REGS_GICR_CID1_LEN    32
#define GICR_LPI_REGS_GICR_CID1_OFFSET 0

#define GICR_LPI_REGS_GICR_CID2_LEN    32
#define GICR_LPI_REGS_GICR_CID2_OFFSET 0

#define GICR_LPI_REGS_GICR_CID3_LEN    32
#define GICR_LPI_REGS_GICR_CID3_OFFSET 0

#define GICR_LPI_REGS_GICR_DEVID_7TO0_LEN    8
#define GICR_LPI_REGS_GICR_DEVID_7TO0_OFFSET 0

#define GICR_LPI_REGS_GICR_JEPID_3TO0_LEN     4
#define GICR_LPI_REGS_GICR_JEPID_3TO0_OFFSET  4
#define GICR_LPI_REGS_GICR_DEVID_11TO8_LEN    4
#define GICR_LPI_REGS_GICR_DEVID_11TO8_OFFSET 0

#define GICR_LPI_REGS_GICR_ARCHREV_LEN       4
#define GICR_LPI_REGS_GICR_ARCHREV_OFFSET    4
#define GICR_LPI_REGS_GICR_USEJEPCODE_LEN    1
#define GICR_LPI_REGS_GICR_USEJEPCODE_OFFSET 3
#define GICR_LPI_REGS_GICR_JEPID_6TO4_LEN    3
#define GICR_LPI_REGS_GICR_JEPID_6TO4_OFFSET 0



#define GICR_LPI_REGS_GICR_CONTINUATIONCODE_LEN    4
#define GICR_LPI_REGS_GICR_CONTINUATIONCODE_OFFSET 0

#endif // __GICR_LPI_REGS_REG_OFFSET_FIELD_H__
